Pipeline DA-converter design and implementation Master of Science Thesis by

Current mode DACs are the popular architectures of today's high-speed data communication industry. Exponential increase of area and power with number of bits pushes this architecture to use some hybrid techniques. The industry leaders use verious matching techniques, optimized layout process, calibrations and the expensive trimming techniques to produce upto 14-bit accu-racy at a very high speed segmented current-steering DACs. This work describes an alternative approach to design a low cost DAC IP core suitable for truely System-on-Chip application usign standard CMOS process. The architecture this core is suitable for wideband Digital-to-Analog converter for System-on-Chip solutions with good performance. It is fully monotonic and also suitable for instru-mentation and imaging applications like PC-Grapics card, set-top boxes. The architecture uses switched capacitor pipelined D/A converter design with Selection Inversion based on gray coded bit stream. A 95dB DC-gain fully differential folded cascode gain-boosted OTA has been de-signed to be used in each pipelined stage. Few combinations of design with the 95dB gain and a 57dB gain OTA with various trade off has been investigated. A typical simulation for a 1