Add to ORKGTo implement high-performance global interconnect without impact-ing the performance of existing blocks, the use of buffer blocks is in-creasingly popular in structured-custom and block-based ASIC/SOC methodologies. Recent works by Cong et al. [6] and Tang and Wong [25] give algorithms to solve the buffer block planning problem. In this paper we address the problem of how to perform buffering of global nets given an existing buffer block plan. Assuming as in [6, 25] that global nets have been already decomposed into two-pin connections, we give a provably good algorithm based on a recent approach of Garg and Könemann [8] and Fleischer [7]. Our method routes connections using available buffer blocks, such that required upper and lower bound...
As the process technology advances into the deep submicron era, interconnect plays a dominant role i...
Abstract- This paper studies the problem of buffer planning for interconnect-centric floorplanning. ...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
To implement high-performance global interconnect without impacting the performance of existing bloc...
Abstract During the routing of global interconnects, macro blocks form useful routing regions which ...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
Closed formed expressions for buffered interconnect delay approximation have been around for some ti...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And...
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron des...
Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several existing bu...
In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream...
We present a staggered buffer connection method that provides flexibility for buffer insertion while...
We present a method for incorporating crosstalk reduction criteria into global routing under an inno...
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As de...
As the process technology advances into the deep submicron era, interconnect plays a dominant role i...
Abstract- This paper studies the problem of buffer planning for interconnect-centric floorplanning. ...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...
To implement high-performance global interconnect without impacting the performance of existing bloc...
Abstract During the routing of global interconnects, macro blocks form useful routing regions which ...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
Closed formed expressions for buffered interconnect delay approximation have been around for some ti...
Interconnect delay has become a critical factor in determining the performance of integrated circuit...
By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And...
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron des...
Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several existing bu...
In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream...
We present a staggered buffer connection method that provides flexibility for buffer insertion while...
We present a method for incorporating crosstalk reduction criteria into global routing under an inno...
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As de...
As the process technology advances into the deep submicron era, interconnect plays a dominant role i...
Abstract- This paper studies the problem of buffer planning for interconnect-centric floorplanning. ...
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken...