Energy-aware error control coding for flash memories

The use of Flash memories in portable embedded systems is ever increasing. This is because of the multi-level storage capability that makes them excellent candidates for high density memory devices. However, cost of writing or pro-gramming Flash memories is an order of magnitude higher than traditional memories. In this paper, we design an al-gorithm to reduce both average write energy and latency in Flash memories. We achieve this by reducing the number of expensive ‘01 ’ and ‘10 ’ bit-patterns during error control coding. We show that the algorithm does not change the er-ror correction capability and moreover improves endurance. Simulations results on representative bit-stream traces show that the use of the proposed algorithm saves, on average, 33 % of write energy and 31 % of latency of Intel MLC NOR Flash memory, and improves the endurance by 24%