Abstract—With advances in process technology, soft errors are becoming an increasingly critical design concern. Owing to their large area, high density, and low operating voltages, caches are worst hit by soft errors. Based on the observation that in multimedia applications, not all data require the same amount of protection from soft errors, we propose a Partially Protected Cache (PPC) architecture, in which there are two caches, one protected and the other unprotected at the same level of memory hierarchy. We demonstrate that as compared to the existing unprotected cache architectures, PPC architectures can provide 47 × reduction in failure rate, at only 1 % runtime and 3 % power overheads. In addition, the failure rate reduction obtained...
Information integrity in cache memories is a fundamental requirement for dependable computing. Conve...
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2016.Energy ...
Abstract—With dramatic scaling in feature size of VLSI technology, the capacity of on-chip L2 cache ...
Abstract Exponentially increasing with technology scaling, soft errors have become a serious design ...
The problem of soft errors caused by radiation events are expected to get worse with technology scal...
The problem of soft errors caused by radiation events are expected to get worse with technology scal...
Low voltage operation and small device sizes reduce the critical charge stored in a SRAM cell making...
As device density grows, each transistor gets smaller and more fragile leading to an overall higher ...
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which inc...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
Cosmic radiation induced soft errors have emerged as a key challenge in computer system design. The ...
Abstract—This paper proposes a new fault tolerant cache organ-ization capable of dynamically mapping...
Continuous technology scaling has brought us to a point, where transistors have become extremely sus...
In this paper, we show that the vulnerability of memory components due to data retention in the pres...
Information integrity in cache memories is a fundamen-tal requirement for dependable computing. Conv...
Information integrity in cache memories is a fundamental requirement for dependable computing. Conve...
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2016.Energy ...
Abstract—With dramatic scaling in feature size of VLSI technology, the capacity of on-chip L2 cache ...
Abstract Exponentially increasing with technology scaling, soft errors have become a serious design ...
The problem of soft errors caused by radiation events are expected to get worse with technology scal...
The problem of soft errors caused by radiation events are expected to get worse with technology scal...
Low voltage operation and small device sizes reduce the critical charge stored in a SRAM cell making...
As device density grows, each transistor gets smaller and more fragile leading to an overall higher ...
Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which inc...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
Cosmic radiation induced soft errors have emerged as a key challenge in computer system design. The ...
Abstract—This paper proposes a new fault tolerant cache organ-ization capable of dynamically mapping...
Continuous technology scaling has brought us to a point, where transistors have become extremely sus...
In this paper, we show that the vulnerability of memory components due to data retention in the pres...
Information integrity in cache memories is a fundamen-tal requirement for dependable computing. Conv...
Information integrity in cache memories is a fundamental requirement for dependable computing. Conve...
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2016.Energy ...
Abstract—With dramatic scaling in feature size of VLSI technology, the capacity of on-chip L2 cache ...