Optimized Mixed Digital-Analog Nearest-Match Circuit for Fully-Parallel Associative Memories

A basic operation of pattern recognition is to find the nearest match between an input-data word of W bit length and a number R of reference-data words [1]. For fast and efficient integration of the nearest-match func-tion a fully-parallel associative-memory has been pro-posed recently [2]. In this fully-parallel associative memory, the search time is primarily determined by the performance of a circuit called winner-line-up amplifier (WLA). The prime goal of the WLA circuitry is to amplify the distance between the winner and the near-est-loser sufficiently so that the following win-ner-take-all (WTA) circuit can decide the winner at bi-nary logic level. Because of the internal capacitances and resistances in the MOS transistors, there is an in-herent delay and the WLA needs considerable time to se