Fast High-level Power Estimation for Control-flow Intensive Designs

In this paper, we present a power estimation technique for control-flow intensive designs that is tailored towards driving iterative high-level synthesis systems, where hundreds of archi-tectural trade-offs are explored and compared. Our method is fast and relatively accurate. The algorithm utilizes the behav-ioral information to extract branch probabilities, and uses these in conjunction with switching activity and circuit capacitance information, to estimate the power consumption of a given ar-chitecture. We test our algorithm using a series of experiments, each geared towards measuring a different indicator. The first set of experiments measures the algorithm’s accuracy when com-pared to the actual circuit power. The second set of experi-ments measures the average tracking index, and tracking in-dex fidelity for a series of architectures. This index measures how well the algorithm makes decisions when comparing the relative power consumption of two architectures contending as low-power candidates. Results indicate that our algorithm achieved an average es-timation error of 11.8 % and an average tracking index of 0.95 over all examples.