Add to ORKGA new approach for sequential circuit test genera-tion is proposed that combines software testing based techniques at the high level with test enhancement tech-niques at the gate level. Several sequences are derived to ensure 100 % coverage of all statements in a high-level VHDL description, or to maximize coverage of paths. The sequences are then enhanced at the gate level to maximize coverage of single stuck-at faults. High fault coverages have been achieved very quickly on several benchmark circuits using this approach.
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
Significant efforts of the test design community have addressed the development of high level test g...
The increasing use of high-level description languages, such as VHDL, to design large VLSI circuits ...
A new approach for sequential circuit test generation is proposed that combines software testing bas...
In this paper, we propose a new high-level test pattern generation technique for sequential circuits...
International audienceIn this paper, we propose a new high-level test pattern generation technique f...
The traditional approaches to test generation made use of the gate level representation of the circu...
The increasing complexity of logic circuits has made the problem of test generation intractable. In ...
Test pattern generation has progressed to a stage at which automatic test generation gives satisfact...
This paper discusses the gate-level automatic test pattern generation (ATPG) methods and techniques ...
A novel approach to testing sequential circuits that uses multi-level decision diagram representatio...
Researchers have proposed different methods for testing digital logic circuits. The need for testing...
Test generation at the gate-level produces high-quality tests but is computationally expensive in th...
This paper presents a switch-level test generation system for synchronous sequential circuits in whi...
I would like to thank the entire staff and my fellow students at the institute for creating a friend...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
Significant efforts of the test design community have addressed the development of high level test g...
The increasing use of high-level description languages, such as VHDL, to design large VLSI circuits ...
A new approach for sequential circuit test generation is proposed that combines software testing bas...
In this paper, we propose a new high-level test pattern generation technique for sequential circuits...
International audienceIn this paper, we propose a new high-level test pattern generation technique f...
The traditional approaches to test generation made use of the gate level representation of the circu...
The increasing complexity of logic circuits has made the problem of test generation intractable. In ...
Test pattern generation has progressed to a stage at which automatic test generation gives satisfact...
This paper discusses the gate-level automatic test pattern generation (ATPG) methods and techniques ...
A novel approach to testing sequential circuits that uses multi-level decision diagram representatio...
Researchers have proposed different methods for testing digital logic circuits. The need for testing...
Test generation at the gate-level produces high-quality tests but is computationally expensive in th...
This paper presents a switch-level test generation system for synchronous sequential circuits in whi...
I would like to thank the entire staff and my fellow students at the institute for creating a friend...
Test generation for sequential VLSI circuits has remained a formidable problem to solve. The problem...
Significant efforts of the test design community have addressed the development of high level test g...
The increasing use of high-level description languages, such as VHDL, to design large VLSI circuits ...