In this paper, we propose a new methodology to inte-grate multiple circuit tranformations and routing processes. More specifically, this paper shows ways to utilize multi-ple choices of circuit transformations in routing processes. First, we introduce a new logic representation that imple-ments all possible wire reconnections implicitly by enhanc-ing global flow optimization techniques. Then we present two approaches for performing routing and wire recon-nection simultaneously: exact approach and practical ap-proach with commercial P/R tools. Since our methods take into account multiple circuit transformations during routing phase where the accurate physical information is available, we can obtain better results than the conventional routin...
A method for performing global routing on an integrated circuit design is disclosed. The integrated ...
This paper presents a collaborative procedure for multiobjective global routing. Our procedure takes...
[[abstract]]In this paper, we consider a board-level routing problem which is applicable to FPGA-bas...
In this paper, we propose a new methodology to integrate circuit transformation into routing. More s...
Abstract—The most popular algorithm for solving the routing problem for field programmable gate arra...
A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of ...
[[abstract]]Global flow optimization (GFO) can perform multiple fanout/fanin wire reconnections at a...
[[abstract]]In this paper, we propose a layout-driven synthesis approach for field programmable gate...
[[abstract]]In this paper, we propose a layout driven synthesis approach for Field Programmable Gate...
177 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986.In this thesis, we study an a...
[[abstract]]©2001 IEICE-The single wire replacement attempts to replace a target wire by another wir...
Interconnect with an insufficient width may be subject to electromigration and eventually cause the ...
This paper describes a three-layer maze router for chip-planning applications. The router contains a...
We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as t...
Interconnect with an insufficient width may be subject to electromigration and eventually cause the ...
A method for performing global routing on an integrated circuit design is disclosed. The integrated ...
This paper presents a collaborative procedure for multiobjective global routing. Our procedure takes...
[[abstract]]In this paper, we consider a board-level routing problem which is applicable to FPGA-bas...
In this paper, we propose a new methodology to integrate circuit transformation into routing. More s...
Abstract—The most popular algorithm for solving the routing problem for field programmable gate arra...
A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of ...
[[abstract]]Global flow optimization (GFO) can perform multiple fanout/fanin wire reconnections at a...
[[abstract]]In this paper, we propose a layout-driven synthesis approach for field programmable gate...
[[abstract]]In this paper, we propose a layout driven synthesis approach for Field Programmable Gate...
177 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986.In this thesis, we study an a...
[[abstract]]©2001 IEICE-The single wire replacement attempts to replace a target wire by another wir...
Interconnect with an insufficient width may be subject to electromigration and eventually cause the ...
This paper describes a three-layer maze router for chip-planning applications. The router contains a...
We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as t...
Interconnect with an insufficient width may be subject to electromigration and eventually cause the ...
A method for performing global routing on an integrated circuit design is disclosed. The integrated ...
This paper presents a collaborative procedure for multiobjective global routing. Our procedure takes...
[[abstract]]In this paper, we consider a board-level routing problem which is applicable to FPGA-bas...