An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks

There is an on-going debate about which consumes less en-ergy: a RAM-tagged associative cache with an intelligent or-der of accessing its tags and ways (e.g. way prediction), or a CAM-tagged high associativity cache. If a CAM search can consume less than twice the energy of reading a tag RAM, it would probably be the preferred option for low-power appli-cations. Based on memory traces | which usually cause tag mismatch within the lower four bits | a new serial CAM or-ganisation is proposed which consumes just 45 % more than a single tag RAM read and is only 25 % slower than the con-ventional, parallel CAM. Furthermore, it can optionally be operated as a parallel CAM, at no speed penalty, and still reduce energy consumption