Parallel modelling paradigm in multimedia applications: Mapping and scheduling onto a multi-processor system-on-chip platform

Multi-processor systems have appeared as a promising alternative to face the difficulties of creating even faster uni-processor systems using latest technologies. Emerg-ing design paradigms such as Multiprocessor System-on-a-Chip (MpSoC) offer high levels of performance and flex-ibility and at the same time promise low-cost, reliable and power-efficient implementations. However, the design com-plexity of such systems have increased tremendously. One source of the complexity stems from highly parallel het-erogeneous nature of the underlying hardware architecture, which poses many challenges for mapping of an applica-tion to the architecture. This motivates the development of a unified programming paradigm that facilitates the map-ping by hiding the architectural complexity and exposing the parallel resources of the architecture. To enable de-sign reuse, such a programming paradigm has to support a smooth translation of sequentially-coded software algo-rithms into their parallel implementations. In this paper we address the parallelization of sequential multimedia appli-cations written in C/C++ for their mapping and schedul-ing onto a flexible MpSoC platform. We show that using our approach an architecture-independent multi-threaded model of a MPEG–2 video decoder algorithm can be ob-tained with only few modifications to an existing sequential implementation of the algorithm. 1