Efficient Built-In Self-Test Techniques for Sequential Fault Testing of Iterative Logic Arrays

Abstract:- In today’s nanometer technology era, more sophicated defect mechanisms might exist in the manufactured integrated circuits which are not covered by traditional fault models. In order to ascertain the quality of shipped chips, more realistic fault models should be addressed. In this paper, we propose built-in self-test (BIST) techniques for iterative logic arrays (ILAs) based on realistic sequential cell fault model (RS-CFM). According to the proposed testability conditions and the adopted fault model, exhaustive SIC (single input change) pairs for a cell are applied to each cell in the ILA. The outputs can be propagated to the primary outputs and then observed. The SIC component generator and output response analyzer are also designed as the BIST circuitry. Due to the regularity of ILAs, the hardware overhead of the BIST circuitry is almost negligible. In order to illustrate our approach, a pipelined array multiplier is used as an example. The number of test pairs for completely testing of the array is only 72. Moreover, the BIST overhead to make it delay fault testable is abou