Automatic test program generation from RT-level microprocessor descriptions

The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two phases: in the first, a library of code fragments (named macros) is generated by hand based on the knowledge of the instruction set, only. In the second phase, an optimization algorithm is run to suitably select macros and values for their parameters. The algorithm only relies on RT-level information, and exploits a suitable RT-level fault model to guide the test program generation. A major advantage of the proposed approach lies in the fact that it does not require any knowledge about the low level implementation of the processor. Experimental results gathered on an i8051 model using a prototypical implementation of the approach show that it is able to generate test programs whose gate-level fault coverage is higher than the one obtained by comparable gate-level ATPG tools, while the computational effort and the length of the generated test program are similar. The method is thus suitable to be applied during the incoming inspection test phase performed on small processors, and for developing implementation-independent test suites for soft IP cores. 1