A Timing-Constrained Algorithm for Simultaneous Global Routing of Multimple Nets

In this paper, we propose a new approach for VLSI intercon-nect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the obser-vation that there are several routing topology flexibilities under timing constraints. These flexibilities are exploited for congestion reduction through a network flow based hierarchical bisection and assignment process. Experimental results on benchmark circuits are quite promising. 1