Gate Sizing and Buffer Insertion for Optimizing Performance

This paper presents a method for optimizing BiCMOS logic networks that exploits the fact that such networks may use a mixture of both CMOS and BiCMOS gates. The method assumes a given network architecture and finds both the logic family and size for each gate so that total delay (power) is minimized subject to a power (delay) constraint. The method views a BiCMOS gate as a type of buffered CMOS gate and selects the logic family for each gale based on a sequence of gatelbuffer sizing optimizations each formulated as a posynomial program. Thus, a high drive BiCMOS gate with a low fan-out can be identifred and replaced with a lower power CMOS gate. For a 0. 8 ~ BiCMOS process, an optimized mixed CMOSIBiCMOS 8-bit adder (8x8 bit multiplier) is found IO be up IO 21 % (1 7%) faster than the optimized CMOS version dissipating the same power.