Generalized Delay Optimization of Resistive Interconnections through an Extension of Logical Effort

Abshrrct: Resistance of VLSI interconnections has become sig-nificant due to large die sizes and sub-mkm geometries in high performance designs. Previous studies have proposed optimal repeater schemes wing slmple buffers for delay optimization of the interconnection. This paper proposes a more general approach that handles arbitrary logic gates as well as buffers. The methodology is based on an extension of the concept of logi-cal effort. The optimization yields proper spacing of the given logk gates, additional repeaters (buffers) required for a given RC line, and sizing of all the gates This approach is applicable to many deslgn situations where existing logic gates must be consid-ered in the overall repeater scheme. I