Bus optimization for low-power data path synthesis based on network flow method

Abstract — Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral level and RT level of design. This paper ad-dresses the problem of minimizing power dissipated in switching of the buses in data path synthesis. Unlike the previous approaches in which minimization of the power consumed in buses has not been considered until operation scheduling is completed, our approach integrates the bus binding problem into scheduling to exploit the impact of scheduling on reduction of power dissipated on the buses more fully and effectively. We accomplish this by formu-lating the problem into a flow problem in a network, and devising an efficient algorithm which iteratively finds maxi-mum flow of minimum cost solutions in the network. Exper-imental results on a number of benchmark problems show that given resource and global timing constraints our de-signs are 22 % power-efficient over the designs produced by a random-move based solution, and 18 % power-efficient over the designs by a clock-step based optimal solution.