Efficient Memory Usage for an 8k-FFT Hardware Implementation

Abstract—In this paper, an FFT (Fast Fourier Transform) hardware circuit is designed for OFDM systems. A memory table permutation method, which can reduce the size of memory storing twiddle factors table, is proposed. The architecture of the FFT circuit is based on split-radix algorithm with SDF (Single-path Delay Feedback) pipeline structure. The bits number of the signal is carefully selected by system simulation to meet the system requirements. As the simulation results shown, the usage of memory can be reduced about 12%. Keywords-fast Fourier transform; single-path delay feedback; orthogonal frequency division multiplexing I