Add to ORKGAbstract A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is logically a four-level Boolean NOR network. By arranging the four logic arrays in a cycle, a compact layout is achieved. Doppio-ESPRESSO, a four-level logic minimization algorithm is developed for WPLA synthesis. No technology mapping, placement or routing is necessary for the WPLA. Area and delay trade-off is absent, because these two goals are usually compatible in WPLA synthesis. 1
© 1991 IEEE. An efficient implementation procedure has been developed for the realization of sequent...
Experiences with heuristics for the state reduction of finite-state machines are presented and two n...
First, an analytical method for the minimization of multiple-valued input Boolean functions is inves...
It describes an automatic design flow to synthesize finte state machines with programmable logic arr...
Abstract A Weinberger array (WA) (Weinberger 1967) synthesis system is described that automatically ...
[[abstract]]We propose a maximum crosstalk minimization algorithm taking logic synthesis into consid...
In this paper, we present a new logic synthesis method for PLA with 2-input logic elements. A PLA wi...
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed....
As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex ...
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can...
Abstract. Circuit realization in one PLA may be unacceptable because of the large number of terms in...
[[abstract]]The use of communication complexity based logic synthesis when configuring programmable ...
[[abstract]]The authors present an approach that combines logic minimization and folding for a progr...
Progress in digital technology has yielded continuing growth in the complexity of circuits that can ...
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance o...
© 1991 IEEE. An efficient implementation procedure has been developed for the realization of sequent...
Experiences with heuristics for the state reduction of finite-state machines are presented and two n...
First, an analytical method for the minimization of multiple-valued input Boolean functions is inves...
It describes an automatic design flow to synthesize finte state machines with programmable logic arr...
Abstract A Weinberger array (WA) (Weinberger 1967) synthesis system is described that automatically ...
[[abstract]]We propose a maximum crosstalk minimization algorithm taking logic synthesis into consid...
In this paper, we present a new logic synthesis method for PLA with 2-input logic elements. A PLA wi...
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed....
As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex ...
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can...
Abstract. Circuit realization in one PLA may be unacceptable because of the large number of terms in...
[[abstract]]The use of communication complexity based logic synthesis when configuring programmable ...
[[abstract]]The authors present an approach that combines logic minimization and folding for a progr...
Progress in digital technology has yielded continuing growth in the complexity of circuits that can ...
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance o...
© 1991 IEEE. An efficient implementation procedure has been developed for the realization of sequent...
Experiences with heuristics for the state reduction of finite-state machines are presented and two n...
First, an analytical method for the minimization of multiple-valued input Boolean functions is inves...