Interconnection Networks

We propose a machine architecture for a high-performance processing node for a message-passing, M IMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffer-ing of messages and a memory-based architecture that permits very fast context switches. Our architecture also includes a novel memory orga-nization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. Simulation re-sults suggest that this architecture reduces message reception overhead by more than an order of magnitude