This paper describes two approaches to the automatic generation of behavioral VHDL models from descriptions written in natural language. Both approaches are based on a modeling style in which behavior is represented by a system of interconnected processes. The first approach employs a semantic grammar to directly generate a single VHDL process from a paragraph written in a restricted English called ModelSpeak. The second approach accepts more general English and generates models consisting of multiple processes
We present a rigorous but transparent semantic definition of VHDL'93 covering the complete sign...
The first step in high level synthesis consists of translating a behavioral specification into its c...
The design and development of process-aware information systems is often supported by specifying req...
This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthes...
This report describes an algorithm for automatically translating BIF system-level behavioral descrip...
One of the major problems within the VHDL based behavioral synthesis is to start the design on highe...
This paper reviews proposals for extensions to VHDL to support high-level modeling and places them w...
Application of formal models provides many benefits for the software and system development, however...
Abstract. Process models are often used to support the understanding and analysis of complex systems...
website : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?tp=&arnumber=410674&isnumber=9191Internatio...
International audienceThe VHDL hardware description language is commonly used to describe Finite Sta...
This report will describe a proposed modeling style for the use of the VHSIC Hardware Description La...
ISBN : 978-1-4244-3341-4International audienceThis paper describes VSYML, a symbolic simulator that ...
Goossens defined a structural operational semantics for a subset of VHDL87 and proved that the paral...
In this paper we address the problem of software generation from a Hardware Description Language (HD...
We present a rigorous but transparent semantic definition of VHDL'93 covering the complete sign...
The first step in high level synthesis consists of translating a behavioral specification into its c...
The design and development of process-aware information systems is often supported by specifying req...
This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthes...
This report describes an algorithm for automatically translating BIF system-level behavioral descrip...
One of the major problems within the VHDL based behavioral synthesis is to start the design on highe...
This paper reviews proposals for extensions to VHDL to support high-level modeling and places them w...
Application of formal models provides many benefits for the software and system development, however...
Abstract. Process models are often used to support the understanding and analysis of complex systems...
website : http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?tp=&arnumber=410674&isnumber=9191Internatio...
International audienceThe VHDL hardware description language is commonly used to describe Finite Sta...
This report will describe a proposed modeling style for the use of the VHSIC Hardware Description La...
ISBN : 978-1-4244-3341-4International audienceThis paper describes VSYML, a symbolic simulator that ...
Goossens defined a structural operational semantics for a subset of VHDL87 and proved that the paral...
In this paper we address the problem of software generation from a Hardware Description Language (HD...
We present a rigorous but transparent semantic definition of VHDL'93 covering the complete sign...
The first step in high level synthesis consists of translating a behavioral specification into its c...
The design and development of process-aware information systems is often supported by specifying req...