Protected IP-Core Test Generation

Design simpli¯cation is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte-gration in a design implies more complex veri¯cation prob-lems. IPs are usually provided with their own test patterns that can be used only by applying design for testability tech-niques onto the chip. Whenever physical faults must be de-tected, this approach is reasonable, even if it implies circuit performance degradation. However, it is completely useless at the design level, when the correct integration of the IPs into the global design must be investigated. At this level, proprietary test sequences must be generated in relation to the actual use of the IPs into the design. In this paper, the SystemC language is exploited to de¯ne a design veri¯ca-tion framework for integration test of IP-cores. Intellectual properties of cores are guaranteed by adopting a client/server simulation architecture and by allowing functional test gen-eration on faulty IP-core models without disclosing their in-ternal structure. The methodology can be applied to mixed descriptions based on VHDL and SystemC, since an abstrac-tion layer has been de¯ned allowing clients and/or servers to be indi®erently described in VHDL or SystemC. Finally, re-mote simulation can be also performed locally to avoid band-width bottleneck and the test generation process can be indif-ferently applied at lower abstraction levels such as RT and gate. 1