Power Efficient Comparators for Long Arguments in Superscalar Processors

Traditional pulldown comparators that are used to implement associative addressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the comparands. As mismatches occur much more frequently than matches in many situations, such circuits are extremely energy–inefficient. In recognition of this inefficiency, a series of dissipate–on–match comparator designs have been proposed to address the power considerations. These designs, however, are limited to at most 8–bit long arguments. In this paper, we examine the designs of energy–efficient comparators capable of comparing arguments as long as 32 bits in size. Such long comparands are routinely used in the load–store queues, caches, BTBs and TLBs. We use the actual layout data and the realistic bit patterns of the comparands (obtained from the simulated execution of SPEC 2000 benchmarks) to show the energy impact from the use of the new comparators. In general, a non–trivial combination of traditional and dissipate–on–match 8–bit comparator blocks represents the most energy–efficient and fastest solution. As an example of this general approach, we show how fast and energy–efficient comparators can be designed for comparing addresses within the load–store queue of a superscalar processor