Extending multicore architectures to exploit hybrid parallelism in single-thread applications

Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of power dissipation and complexity. Current chip multi-processors increase throughput by utilizing multiple cores to perform computation in parallel. These designs provide real benefits for server-class applications that are explic-itly multi-threaded. However, for desktop and other sys-tems where single-thread applications dominate, multicore systems have yet to offer much benefit. Chip multiproces-sors are most efficient at executing coarse-grain threads that have little communication. However, general-purpose ap-plications do not provide many opportunities for identifying such threads, due to frequent use of pointers, recursive data structures, if-then-else branches, small function bodies, and loops with small trip counts. To attack this mismatch, this pa-per proposes a multicore architecture, referred to as Voltron, that extends traditional multicore systems in two ways. First, it provides a dual-mode scalar operand network to enable efficient inter-core communication and lightweight synchro-nization. Second, Voltron can organize the cores for execu-tion in either coupled or decoupled mode. In coupled mode, the cores execute multiple instruction streams in lock-step to collectively function as a wide-issue VLIW. In decoupled mode, the cores execute a set of fine-grain communicating threads extracted by the compiler. This paper describes the Voltron architecture and associated compiler support for or-chestrating bi-modal execution.