Abstract. This paper addresses the design of a Reprogrammable Combinatorial Processor (RCP) on the basis of reconfigurable circuits such as FPGA. The RCP is intended to be used for solving different combinatorial problems formulated over discrete matrices. From a structural point of view the RCP is a composition of a Reconfigurable Control Unit (RCU) and a Reconfigurable Function Unit (RFU). Each unit consists of hardwired (fixed) and programmable components. The paper considers and analyses methods, which can be used for logic synthesis and optimisation of RCP based on such decomposition
This paper presents a method to implement a reconfig-urable logic array on an FPGA. To design circui...
This paper presents the idea of the reconfigurable general-purpose processor implemented as dynamica...
This paper discusses the problem of minimizing the reconfiguration cost of some types of reconfigur...
The paper introduces RHS model for combinatorial computations that describes partitioning of the pro...
Abstract. The paper suggests architecture of a reconfigurable processor, which can be customized for...
The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers i...
This book presents the original concepts and modern techniques for specification, synthesis, optimis...
This paper discusses an approach for solving combinatorial problems by combining software and dynami...
Combinatorial problems that have to be solved in modern intelligent control systems frequently posse...
In this paper we present a hardware design technique which utilises runtime reconfiguration for a pa...
The goal of this paper is to promote application of logic synthesis methods and tools in different t...
The book is composed of two parts. The first part introduces the concepts of the design of digital s...
The paper suggests a novel method for implementing recursive algorithms in hardware. The required su...
Reconfigurable Circuit (RC) platforms can be configured to implement complex combinatorial and seque...
Abstract-Field programmable gate arrays (FPGA) are increasingly being used in the high performance a...
This paper presents a method to implement a reconfig-urable logic array on an FPGA. To design circui...
This paper presents the idea of the reconfigurable general-purpose processor implemented as dynamica...
This paper discusses the problem of minimizing the reconfiguration cost of some types of reconfigur...
The paper introduces RHS model for combinatorial computations that describes partitioning of the pro...
Abstract. The paper suggests architecture of a reconfigurable processor, which can be customized for...
The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers i...
This book presents the original concepts and modern techniques for specification, synthesis, optimis...
This paper discusses an approach for solving combinatorial problems by combining software and dynami...
Combinatorial problems that have to be solved in modern intelligent control systems frequently posse...
In this paper we present a hardware design technique which utilises runtime reconfiguration for a pa...
The goal of this paper is to promote application of logic synthesis methods and tools in different t...
The book is composed of two parts. The first part introduces the concepts of the design of digital s...
The paper suggests a novel method for implementing recursive algorithms in hardware. The required su...
Reconfigurable Circuit (RC) platforms can be configured to implement complex combinatorial and seque...
Abstract-Field programmable gate arrays (FPGA) are increasingly being used in the high performance a...
This paper presents a method to implement a reconfig-urable logic array on an FPGA. To design circui...
This paper presents the idea of the reconfigurable general-purpose processor implemented as dynamica...
This paper discusses the problem of minimizing the reconfiguration cost of some types of reconfigur...