Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to pre-dict the delay distribution of an interconnect pipeline stage and the slew distributions of all the nets in the circuit. Also, a buffer sizing and re-placement algorithm is presented to minimize the area of interconnect pipelines while meeting the delay and slew constraints. Experiments show that ig-noring location dependent variation can cause a timing yield loss of 8.8 % in a delay limited circuit, and the area can be improved by over 10 % when the location depen-dent variation and residual random variation are under-stood and separated. Furthermore, under equivalent area, a...
As Moore’s law is followed closely over the past decades, down-scaling of transistor structure lea...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
With the advance of fabrication technology into the deep sub-micron era process parameter variations...
Abstract—Under inter-die and intra-die parameter variations, the delay of a pipelined circuit follow...
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage....
The growing impact of process variation on circuit performance requires statistical design approache...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
In this paper, we propose a novel and efficient algorithm for modelling sub-65 nm clock interconnect...
In this paper, we propose a novel and efficient algorithm for modelling sub-65 nm clock interconnect...
Due to continuous quest for greater throughput, pipelined circuits are used to support multi-cycle p...
Abstract: This paper considers the problem of interconnect wire delay in digital integrated circuits...
In nanometer designs, interconnect delay dominates the overall circuit delay, and hence design focus...
In nano-scaled large variations in process parameters produces wide delay spread in high performance...
As Moore’s law is followed closely over the past decades, down-scaling of transistor structure lea...
The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissibl...
As Moore’s law is followed closely over the past decades, down-scaling of transistor structure lea...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
With the advance of fabrication technology into the deep sub-micron era process parameter variations...
Abstract—Under inter-die and intra-die parameter variations, the delay of a pipelined circuit follow...
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage....
The growing impact of process variation on circuit performance requires statistical design approache...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
In this paper, we propose a novel and efficient algorithm for modelling sub-65 nm clock interconnect...
In this paper, we propose a novel and efficient algorithm for modelling sub-65 nm clock interconnect...
Due to continuous quest for greater throughput, pipelined circuits are used to support multi-cycle p...
Abstract: This paper considers the problem of interconnect wire delay in digital integrated circuits...
In nanometer designs, interconnect delay dominates the overall circuit delay, and hence design focus...
In nano-scaled large variations in process parameters produces wide delay spread in high performance...
As Moore’s law is followed closely over the past decades, down-scaling of transistor structure lea...
The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissibl...
As Moore’s law is followed closely over the past decades, down-scaling of transistor structure lea...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
With the advance of fabrication technology into the deep sub-micron era process parameter variations...
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