A New Buffer-Memory Architecture for FFT Computation

Abstract — Memory-based designs of the fast Fourier transform (FFT) processor are attractive for single-chip implementation. Basically, their architectures can be divided into three types: single-memory design, dual-memory design, and buffer-memory design. Among them, the buffer-memory design can balance the trade-off between memory size and control circuit complexity. In this paper, we present a new buffer-memory architecture for realizing the radix-2 decimation-in-time N-point FFT algorithm. As compared with previous related works, the proposed design reaches the same throughput performance of two transform samples per log2N+1 clock cycles and 100 % utilization efficiency in butterfly unit with fewer ROM access times of N-2. It is rather attractive for long-length FFT applications, such as very-high-rate digital subscriber lines and digital video broadcasting