The Scalability of Scheduling Algorithms for Unpredictably Heterogeneous CMP Architectures

Future chip multiprocessors (CMPs) will be expected to deliver robust performance in the face of manufacturing process variations and hard errors. While prior research has addressed how to keep these chips functional, these degraded CMPs may still be unusable because of lost performance and power efficiency. The unpredictable nature of the variability and faults will create dynamic heterogeneity among the cores of these CMPs. In prior work, we developed scheduling algorithms that mitigate the impact of core degradation by appropriately matching applications in the workload with cores of differing capabilities. In this paper, we study the scalability of these algorithms in CMPs ranging from four to sixty-four cores. Our results show that our algorithms which perform multiple exploration steps in parallel have greater potential to scale to larger CMP organizations