Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies

Variation in transistor characteristics and particularly threshold voltage (Vt) has emerged as a major challenge for circuit design in scaled technologies. Process variations result in increased mismatch among neighboring transistors which can affect the correct functionality of circuits such as sense amplifiers. In this paper, we will analyze the impact of process variations on sense amplifier circuits in detail. We will explore statistical design and optimization techniques based on transistor sizing to improve the reliability of sense amplifiers under process variations. Furthermore, we will exploit dual Vt option to enhance the sense amplifier robustness. According to simulation results in a 70nm process, by optimal transistor sizing and dual Vt assignment, failure probability of sense amplifiers can be greatly reduced (by more than 80%). 1