Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder

A cost-efficient realisation of an advanced multimedia system requires high-level memory optimisations to deal with the dominant memory cost. This typically results in more efficient code for both power and system bus load. However, also significant performance improvement can be achieved when carefully optimising the address functional-ity. This paper shows how the nature of this addressing code and the related control flow allows to transform the complex index, iterator and condition expressions into efficient arith-metic. We apply our ADdress OPTimisation (ADOPT) de-sign technology to a low power memory optimised MPEG-4 decoder. When mapped on popular programmable multi-media processor architectures, we obtain a factor of 2 in performance gain. 1