Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances that are in the same order of magnitude as intrinsic capacitances as far as deep-submicron designs are concerned. This trend has been recognized in recent research work. In this work, we present a physical model that takes into account inter-wire capacitances. Subsequently we propose a novel encoding scheme based on this physical model and targeted for address buses. We demonstrate that our encoding method improves power consumption by up to 62.5 % and thus is exceeding all current approaches including our own previous one. In addition, the hardware of the bus enc...
The power dissipated by system-level buses is the largest contribution to the global power of compl...
AbstractEnergy dissipation of interconnects is becoming a bottle neck for high performance integrate...
A data-distribution and bus-structure aware methodology for the design of coding schemes for low-pow...
In microprocessor-based systems, large power savings can be achieved through reduction of the transi...
Abstract The energy dissipation associated with driving long wires accounts for a significant fracti...
Abstract—An ever more significant fraction of the overall power dissipation of a network-on-chip (No...
Now a day’s VLSI has become the backbone of all types of designs. Interconnect plays an increasing r...
Abstract. Crosstalk causes logical errors due to data dependent delay degrada-tion as well as energy...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
The power dissipated by system-level buses is the largest contribution to the global power of comple...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
136 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001.Since intermodule buses and i...
Abstract —Power consumption and delay are two of the most important constraints in current-day on-ch...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
The power dissipated by system-level buses is the largest contribution to the global power of compl...
AbstractEnergy dissipation of interconnects is becoming a bottle neck for high performance integrate...
A data-distribution and bus-structure aware methodology for the design of coding schemes for low-pow...
In microprocessor-based systems, large power savings can be achieved through reduction of the transi...
Abstract The energy dissipation associated with driving long wires accounts for a significant fracti...
Abstract—An ever more significant fraction of the overall power dissipation of a network-on-chip (No...
Now a day’s VLSI has become the backbone of all types of designs. Interconnect plays an increasing r...
Abstract. Crosstalk causes logical errors due to data dependent delay degrada-tion as well as energy...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and sy...
The power dissipated by system-level buses is the largest contribution to the global power of comple...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
136 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2001.Since intermodule buses and i...
Abstract —Power consumption and delay are two of the most important constraints in current-day on-ch...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
The power dissipated by system-level buses is the largest contribution to the global power of compl...
AbstractEnergy dissipation of interconnects is becoming a bottle neck for high performance integrate...
A data-distribution and bus-structure aware methodology for the design of coding schemes for low-pow...