Trade-Offs in Multiplier Block Algorithms for Low Power Digit-Serial FIR Filters

Abstract:- In this paper trade-offs in digit-serial multiplier blocks are studied. Three different algorithms for realization of multiplier blocks are compared in terms of complexity and adder depth. Among the three algo-rithms is a new algorithm that reduces the number of shifts while the number of adders is on average the same. Hence, the total complexity is reduced for multiplier blocks implemented using digit-serial arithmetic, where shift operations have a hardware cost. An example implementation is used to compare the power consumption for five approaches: the three algorithms, using separate multipliers based on CSD representation, and an algo-rithm based on subexpression sharing. The design of low power multiplier blocks is shown to be a more compli-cated problem than to reduce the complexity. A main factor that needs to be considered is adder depth. Furthermore, digit-serial shifts will reduce glitch propagation