Interconnect scaling to deep submicron processes pre-sents many challenges to today’s CAD flows. A recent analy-sis by Sylvester and Keutzer examined the behavior of average length wires under scaling, and controversially con-cluded that current CAD tools are adequate for future mod-ule-level designs. In our work, we show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all rea-sonable scaling assumptions. However, examining only aver-age length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scal-ing assumptions, the number of long wires will inc...
This lecture covers the impact of technology scaling on wire delay, and how this affects memory acce...
A comprehensive review of challenges and potential solutions associated with the impact of downscali...
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance ef...
The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI te...
Concern about the performance of wires in scaled technologies has led to research exploring other co...
Wires have become a major source of bottleneck in current VLSI designs, and wire length prediction i...
[[abstract]]Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI inter...
Technology scaling reduces gate delays while wire delays may increase. Our work studies the interact...
The work in this paper addresses the need to evaluate the impact of emerging interconnect technologi...
acute problem in the interconnect area as IC feature sizes continually scale below 32 nm. When the c...
The recent electronics revolution has been fueled by the decades-long trend of exponential growth in...
We discuss interconnect parasitic extraction in the nanometer domain using the ITRS 2005 roadmap for...
Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing ...
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow...
The trend in deep-submicron integrated circuit design is towards reduced line widths together with l...
This lecture covers the impact of technology scaling on wire delay, and how this affects memory acce...
A comprehensive review of challenges and potential solutions associated with the impact of downscali...
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance ef...
The roots of this book, and of the new research field that it defines, lie in the scaling of VLSI te...
Concern about the performance of wires in scaled technologies has led to research exploring other co...
Wires have become a major source of bottleneck in current VLSI designs, and wire length prediction i...
[[abstract]]Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI inter...
Technology scaling reduces gate delays while wire delays may increase. Our work studies the interact...
The work in this paper addresses the need to evaluate the impact of emerging interconnect technologi...
acute problem in the interconnect area as IC feature sizes continually scale below 32 nm. When the c...
The recent electronics revolution has been fueled by the decades-long trend of exponential growth in...
We discuss interconnect parasitic extraction in the nanometer domain using the ITRS 2005 roadmap for...
Growing number of excessively long on-chip wires in modern monolithic ICs is a byproduct of growing ...
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow...
The trend in deep-submicron integrated circuit design is towards reduced line widths together with l...
This lecture covers the impact of technology scaling on wire delay, and how this affects memory acce...
A comprehensive review of challenges and potential solutions associated with the impact of downscali...
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance ef...