Interconnect Synthesis in High Speed Digital VLSI Routing

The advent of the nanotechnology has introduced new challenges and non-conventional problems to high speed digital Very Large Scale Integrated (VLSI) design. Moreover, the resultant progress of manufacturing technology is widening the gap between current Computer Aided Design (CAD) tools and VLSI technologies. This is reflected clearly in the IC design process where the Integrated Circuit (IC) flow has become very iterative, especially in the back end phase. These returns to the complexity of placement and routing phases, and the inadequate approximations used for interconnect modeling and characterization. In this paper, we introduce a new performance-wise approach that combines connection graphs with a basic area routing algorithm to complete the routing without or with minimal iterations. In this approach, the routing elements are ordered with respect to its space not with respect to their relative position, to modify its complexity and optimize memory requirements to fit the problem in hand. This can help to yield a time complexity of)log(log SO and a memory complexity in worst case)(SO, where S is the size of the space. Instead of employing the traditional flow that uses inaccurate interconnect models and characterization techniques, and then analyze the output to point out errors in the resulting layout, we propose Interconnect Synthesis as a framework. Within this framework, we introduce an enhanced routing algorithm that outperforms traditional routers and present a more accurate interconnect modeling and signal characterization techniques fo