Implementation of a Low-Power 200 MSample/s 12-bit Pipelined ADC Macro Using Deep-Submicron Digital CMOS Technology

In this paper, we present the design, verification, system integration and the physical realization of a fully integrated high-speed analog-digital converter (ADC) macro block with 12-bit accuracy. The entire circuit architecture is built with a modular approach, consisting of identical units organized into an easily expandable pipeline chain. A bit-overlapping technique has been employed for digital error correction between the pipeline stages to reduce possible errors that occur during analog signal processing. The circuit has been realized using 0.18 µm digital CMOS technology. The ADC macro presented in this work is capable of operating at sampling frequencies of up to 200 MHz, and still can achieve the nominal bit-resolution that was intended for 12-bit accuracy. The maximum range of the input signal amplitude can be as high as 1.6 Vpp, with 1.8 V supply voltage. The overall power consumption is estimated as 67.5 mW at 200 MHz sampling rate. The overall silicon area of the ADC is approximately 0.25 mm2. The presented ADC architecture qualifies as a very versatile embedded macro block that can be used in deep-submicron SoC design