As customer requirements reduce the maximum product defects allowed to less than one part-per-million, identifying the source of the occasional defect during wafer processing becomes more challenging. We observed a defect on wafers we call “via rings”. This defect occurs when the street photoresist does not sufficiently protect the plated gold film at the top edge of the through wafer vias during the street etch process. This paper discusses the use of an additional step during the street resist coat process to ensure that the resist properly protects the edges of the vias during the etch process
textIn 1960's Gordon Moore predicted that the increase in the number of components in integrated cir...
In the electron beam lithography process, one of the initial steps is to coat the substrate (i.e., t...
Extreme ultraviolet lithography (EUVL) is expected to be used in device manufacturing starting at 32...
Defects in photolithographic processing account for large yield losses in semiconductor device fabri...
Conclusion We have demonstrated that poor-quality etch masks on the InP wafer surface can be a cause...
The development of 100-nm design rule technologies is currently taking place in many R&D facilit...
GaAs devices in our factory employ through wafer via technology. Since the wafers are electrically t...
Improved lithographic processes have led to the high packing densities of present integrated circuit...
The predominant factors that contribute to the formation of polymer on the bottom and sidewalls of v...
Most defect signatures on wafers are caused by faulty tools. If these defects are not captured by in...
In patterning the via-hole, uneven hole-size and missing-hole defects were identified through after ...
stripper, gallium arsenide (GaAs), and metal lift-off The occurrence of galvanic corrosion on compou...
Positive resist coated wafers were Immersed in a dilute alkaline base developer, such as 5:1 AZ351, ...
For the production of silicon photo-transducers (PhT) the acquisition of epitaxial compositions (EC)...
This Project is to reduce the yield loss realized at In-circuit testing for surface mount solder def...
textIn 1960's Gordon Moore predicted that the increase in the number of components in integrated cir...
In the electron beam lithography process, one of the initial steps is to coat the substrate (i.e., t...
Extreme ultraviolet lithography (EUVL) is expected to be used in device manufacturing starting at 32...
Defects in photolithographic processing account for large yield losses in semiconductor device fabri...
Conclusion We have demonstrated that poor-quality etch masks on the InP wafer surface can be a cause...
The development of 100-nm design rule technologies is currently taking place in many R&D facilit...
GaAs devices in our factory employ through wafer via technology. Since the wafers are electrically t...
Improved lithographic processes have led to the high packing densities of present integrated circuit...
The predominant factors that contribute to the formation of polymer on the bottom and sidewalls of v...
Most defect signatures on wafers are caused by faulty tools. If these defects are not captured by in...
In patterning the via-hole, uneven hole-size and missing-hole defects were identified through after ...
stripper, gallium arsenide (GaAs), and metal lift-off The occurrence of galvanic corrosion on compou...
Positive resist coated wafers were Immersed in a dilute alkaline base developer, such as 5:1 AZ351, ...
For the production of silicon photo-transducers (PhT) the acquisition of epitaxial compositions (EC)...
This Project is to reduce the yield loss realized at In-circuit testing for surface mount solder def...
textIn 1960's Gordon Moore predicted that the increase in the number of components in integrated cir...
In the electron beam lithography process, one of the initial steps is to coat the substrate (i.e., t...
Extreme ultraviolet lithography (EUVL) is expected to be used in device manufacturing starting at 32...