Performance Tuning of the Fast Fourier Transform on a Multi-core Architecture

We are now entering the multi-core era, many multi-core chips are designed and manufactured by various vendors, such as Intel, AMD and Sun etc. IBM Cyclops-64(C64) is a multi-core archi-tecture that provides massive on-chip parallelism, massive on-chip bandwidth, and multiple level memory hierarchy. This type of multi-core architecture presents big challenges to application devel-opers and system software designers on how to exploit the thread level parallelism(TLP) provided by the multi-core chips. While a lot of researchers believe that multi-core architecture will become the mainstream in the future, there are only a few studies about the application development on those advanced architec-tures have been reported. The emerging multi-core architectures not only unveil opportunities of massive on-chip paral-lelism through hardware support, but also present great challenges to application developers and system software designers. In this paper, we report our experience of optimizing the Fast Fourier Transform (FFT) on the IBM Cyclops-64 (C64) architecture, a novel multi-core architecture con-sisting of 160 threads, an explicit memory hierarchy, and an on-chip interconnection network