LEAKAGE ENERGY REDUCTION IN ON-CHIP MICROPROCESSOR CACHES

Leakage power is becoming dominant part of the micro-processor chip power budget as feature size shrinks. Leakage energy consumption is of particular concern in memory structures, such as on-chip caches, for large scale transistors and rare access. Chipmakers have pro-posed many low leak circuit techniques for cache leak-age control, in which gated-vdd and DVS are two effec-tive methods. In this paper, based on these two circuits we propose two architectural mechanisms, LRU-assist and ADSR, to reduce leakage energy consumption in on-chip cache hierarchies. LRU-assist decay combines time-based decay with existing LRU information to aggres-sively cut off lines in L1 cache. ADSR (Always Drowsy Speculatively Recover) puts the whole L2 cache in low leakage state all the time and speculatively recovers line’s supply voltage using prefetch-like mechanism. We run SPEC CPU2000 benchmarks on a cycle accurate simulator to evaluate their efficiency. LRU-assist decay reduces L1 cache leakage power by 55 % on average and improves EDP by 2%. ADSR with next-line recover reduces L2 cache leakage power by 66 % on average and improves EDP by 47%