An Area-Efficient Systolic Architecture for Real-Time VLSI

An area-eficzent systolic architecture for real-time, programmable-coeBcient jinite impulse response (FIR) filters is presented. A technique called pipelined clustering i s introduced t o derive the architecture in which a number of jilter t a p computations are multi-plexed in an appropriately pipelined processor. This multiplezing is m a d e possible b y the fact that the pro-cessor is clocked at the highest possible frequency wnder the given. technology and design constraints. Reduction in hardware proportional to the ratio of data arrival period and clock period is ach,ieved. The proposed sys-tolic architecture is 100 % eficient and has the sam,e throughput and latency and approximately the same power dissipation as a n unclustered array. The archi-tecture i s completely specified, including a description, o f the m.uHip1exer.s and synchron.isation delays that are requ ired.