Sensitivity Factor Analysis in the Bias Circuits with FET

Abstract:- The paper proposes a procedure to calculate the sensitivity factors of the quiescent drain current of a FET operating in the active region in conjunction with a general-purpose circuit simulator. Unlike the procedure developed for the sensitivity factors of the quiescent collector current in BJT, this one is not based on the drain current expression of the FET. We showed that the sensitivity factors of the quiescent drain current can be calculated by repeated simulations of the bias circuit modified according to the change of a parameter value