Abstract — In this paper, an efficient linear time algorithm TACO is proposed for the first time to minimize the worst case clock skew in the presence of on-chip thermal variation. TACO, while tries to minimize the worst case clock skew, also attempts to minimize the clock tree wirelength by building up merging diamonds in a bottom-up manner. As an output, TACO provides balanced merging points and the modified clock routing paths to minimize the worst case clock skew under thermal variation. Experimental results on a set of standard benchmarks show 50- 70 % skew reduction with less than 0.6 % wirelength overhead. I
Power densities and temperatures in today's high performance circuits have reached alarmingly high l...
Negative bias temperature instability (NBTI) has emerged as a major concern not only to the function...
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock ga...
Temperature variation in microprocessors is a workload dependent problem. In such a design, the cloc...
The existence of non-uniform thermal gradients on the substrate in high performance IC's can signifi...
The trend of growing density on chips has increases not only the temperature in chips but also the g...
Thermal issues are a primary concern in the three-dimensional integrated circuit (3D IC) design. Thi...
Modern computing system applications or workloads can bring significant non-uniform temperature grad...
Abstract — In this paper, we study the buffered clock tree synthesis problem under thermal variation...
Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliabil...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
Eliminating timing violations using clock tree optimization (CTO) persist to be a tedious problem in...
Clock distribution is vital to all synchronous integrated circuits; a poor clock distribution networ...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
Power densities and temperatures in today's high performance circuits have reached alarmingly high l...
Negative bias temperature instability (NBTI) has emerged as a major concern not only to the function...
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock ga...
Temperature variation in microprocessors is a workload dependent problem. In such a design, the cloc...
The existence of non-uniform thermal gradients on the substrate in high performance IC's can signifi...
The trend of growing density on chips has increases not only the temperature in chips but also the g...
Thermal issues are a primary concern in the three-dimensional integrated circuit (3D IC) design. Thi...
Modern computing system applications or workloads can bring significant non-uniform temperature grad...
Abstract — In this paper, we study the buffered clock tree synthesis problem under thermal variation...
Chip heating and nonuniform distribution of hot and cool zones on the die negatively affect reliabil...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
Eliminating timing violations using clock tree optimization (CTO) persist to be a tedious problem in...
Clock distribution is vital to all synchronous integrated circuits; a poor clock distribution networ...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
Power densities and temperatures in today's high performance circuits have reached alarmingly high l...
Negative bias temperature instability (NBTI) has emerged as a major concern not only to the function...
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock ga...