MD5 Hash Algorithm Hardware Realization on a Reconfigurable FPGA

In this paper, the hardware implementation of the MD5 algorithm on reconfigurable devices, such as FPGAs, is investigated. These hardware devices provide high performance at low cost, which makes them suitable for cryptographic and cryptanalytic purposes. The high performance of the implementation is the main goal of the design presented herein. The need of secure internet communication has given rise to message authentication as an essential technique to verify the integrity of received data. Every cryptographic system, e.g., e-mail applications, bank transactions, etc, uses hash functions for message authentication purposes. With the advent of public key cryptography and digital signature schemes, cryptographic hash functions gained much more prominence. In IPSec hash functions are utilized to achieve data integrity assurance, data origin and message content authentication. Using Hash Functions it is possible to produce a fixed length fingerprint that depends on the whole message and ensures that it has not been altered during an insecure transmission. Through the hashing procedure message length is effectively reduced and as