A Novel Specification Model for IP-based Design

The proposed specification method denoted as hierar-chical CoDesign Model allows a hierarchical system level specification of distributed embedded systems including both definition and reuse of IP cores. Input/Output Rela-tions are introduced as a very general and powerful means of encapsulating internal implementation details and of de-scribing data as well as control flow information on differ-ent levels of abstraction. Two novel algorithms are pro-posed, which allow to derive dynamically task descriptions for the IP encapsulation as well as flat specification mod-els for design space exploration on different levels of de-tail. This reduces considerably the descriptive complexity of specifications and therewith the execution times of syn-thesis and design space exploration algorithms. 1