Leakage minimization of nano-scale circuits in the presence of systematic and random variations

This paper presents a novel gate sizing methodology to mini-mize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The exist-ing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the ob-jective function is O(|N |2) and that of evaluating the delay constraints is O(|N | + |E|) for a circuit with |N | gates and |E | wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution