Design of a Wide Band Frequency Synthesizer Based on

Abstract—A wide-band frequency synthesizer based on time-to-digital (TDC) and digital-to-voltage (DVC) conversion techniques is proposed here. The proposed frequency synthesizer has the ca-pabilities of jitter reduction and large bandwidth, making it more robust for high-frequency applications. A test chip is designed and fabricated in 0.6- m CMOS single-poly triple-metal process. Here, the novel DVC circuit is realized by tristate inverters, where the resolution can achieve 0.2 mV. Control stability of jitter can im-prove about 24 dB by exploiting the TDC-based controller. In order to achieve high output frequency and large output range, an analog voltage-controlled oscillator is designed to provide a locked range from 900 to 1900 MHz with 22 kHz resolution at 3.3 V. Simula-tion and test results show that the proposal can work as expected. Moreover, the TDC-based controller can be treated as soft IP to speed up turnaround time. Index Terms—ADPLL, clock generator, DVC, frequency synthe-sizer, IP, mixed mode, SOC, TDC. I