Logic synthesis for AND-XOR-OR type sense-amplifying PLA

In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve low-power dissipation and high-speed operation by using latch sense-amplifiers and a charge sharing scheme. In addition, 2-input XOR function is conveniently implemented in place of the conventional AND/OR planes. Therefore it can real-ize some classes of logic functions in a smaller circuit area. Since the proposed method makes full use of the existing two-level logic minimization algorithms, it can handle large circuits such as 64-input Boolean function. The method has been implemented and the experimental results are pre-sented. The experimental results show that some classes of Boolean functions can become much smaller and hence we can obtain significantly faster circuits than conventional PLAs with a small area penalty. 1