Signature Rollback – A Technique for Testing Robust Circuits

Dealing with static and dynamic parameter varia-tions has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a robust design has become mandatory. However, standard structural test proce-dures still address classical fault models and cannot deal with the non-deterministic behavior caused by parameter variations and other reasons. Chips may be rejected, even if the test reveals only non-critical fail-ures that could be compensated during system opera-tion. This paper introduces a scheme for embedded test, which can distinguish critical permanent and non-critical transient failures for circuits with time redun-dancy. To minimize both yield loss and the overall test time, the scheme relies on partitioning the test into shorter sessions. If a faulty signature is observed at the end of a session, a rollback is triggered, and this par-ticular session is repeated. An analytical model for the expected overall test time provides guidelines to deter-mine the optimal parameters of the scheme.