Explicit Gate Delay Model for Timing Evaluation

Delay evaluation is always a crucial concern in the VLSI de-sign and it becomes increasingly more critical in the nowa-days deep-submicron technology. To obtain an accurate de-lay value, the gate modeling is a key issue. As the VLSI fea-ture size scaling down and meanwhile operating frequency increasing, the modeling work becomes more difficult than ever for high-performance digital ICs. Nevertheless, most conventional techniques of gate modeling are based on the switch-resistor model (i.e., a voltage source concatenating a driving resistance), which can only capture the gate charac-teristic in its switching region. Hence, these modeling tech-niques have to decouple the gate with its interconnects and compute a piecewise linear function for the driving source in the iterative computation of effective capacitance [1, 3, 4]. Since the driving source of the model is dependent on gate load, when the design modification affects the load, the gate has to be modeled again almost from the beginning for a new timing analysis. The efficiency will be deteriorated in synthesis loops due to this. In this paper, we present an explicit gate delay model, which is not sensitive to gate load and can be pre-computed before timing analysis and synthesis. Thus, the repetition of modeling work is totally unnecessary even when the gate load keeps on changing in the performance optimization procedure. The efficiency is certainly improved in the synthesis/optimization loops. The advantage is attributed to using a second-order circuit as the model base. This two-pole approach also certifies the model to yield an accurate result to match the non-linear output of gate. ∗This work was partially supported by the National Science Foundation under grant CCR-0244236