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Abstract — The communication sub-system of complex IC systems is increasingly critical for achieving system perfor-mance. Given this, it is important that the on-chip communi-cation architecture should be included in any quantitative eval-uation of system design during design space exploration. While there are several mature methodologies for the modeling and evaluation of architectures of processing elements, there is rel-atively little work done in modeling of an extensive range of on-chip communication architectures, and integrating this into a single modeling and simulation environment combining pro-cessing element and on-chip communication architectures. This paper describes a modeling framework with accompanying sim-ulation tools that attempts to fill this gap. Based on an analy-sis of a wide range of on-chip communication architectures, we describe how a specific hierarchical class library can be used to develop new on-chip communication architectures, or vari-ants of existing ones with relatively little incremental effort. We demonstrate this through three case studies including two com-mercial on-chip bus systems and an on-chip packet switching network. Here we show that through careful analysis and con-struction it is possible for the modeling environment to support the common features of these architectures as part of the library and permit instantiation of the individual architectures as vari-ants of the library design. As part of this methodology we also show how different levels of abstraction of the model can be sup-ported and viewed as different variants that can be used in an accuracy versus simulation time trade-off. I