Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Cir-cuit simulation is carried out in the inner loop of this tuning proce-dure. Automating the transistor sizing process is an important step towards being able to rapidly design high-performance, custom cir-cuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accom-modated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular lay-outs. Bounds on transistor widths are supported. JiffyTune uses L...
Analog designers are interested in using optimization tools which may automate the process of transi...
The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, ca...
Determining the device width to length ratios has typically been an iterative process for the custom...
The relentless push for high performance in custom dig-ital circuits has led to renewed emphasis on ...
[[abstract]]A combined heuristic and mathematical programming approach to transistor sizing is prese...
[[abstract]]A combined heuristic and mathematical programming approach to transistor sizing is prese...
This paper describes a novel algorithm for automatic transistor sizing which is one technique for im...
This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizi...
The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance spe...
Blesken M, Rückert U, Steenken D, Witting K, Dellnitz M. Multiobjective optimization for transistor ...
Abstract: Circuit sizing problem in application specific analog integrated circuit design is in most...
We use constrained optimization to select operating parameters for two circuits: a simple 3-transist...
The analog circuit sizing can be viewed as a constrained optimization problem. Evolutionary algorith...
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our ...
Analog designers are interested in using optimization tools which may automate the process of transi...
Analog designers are interested in using optimization tools which may automate the process of transi...
The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, ca...
Determining the device width to length ratios has typically been an iterative process for the custom...
The relentless push for high performance in custom dig-ital circuits has led to renewed emphasis on ...
[[abstract]]A combined heuristic and mathematical programming approach to transistor sizing is prese...
[[abstract]]A combined heuristic and mathematical programming approach to transistor sizing is prese...
This paper describes a novel algorithm for automatic transistor sizing which is one technique for im...
This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizi...
The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance spe...
Blesken M, Rückert U, Steenken D, Witting K, Dellnitz M. Multiobjective optimization for transistor ...
Abstract: Circuit sizing problem in application specific analog integrated circuit design is in most...
We use constrained optimization to select operating parameters for two circuits: a simple 3-transist...
The analog circuit sizing can be viewed as a constrained optimization problem. Evolutionary algorith...
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our ...
Analog designers are interested in using optimization tools which may automate the process of transi...
Analog designers are interested in using optimization tools which may automate the process of transi...
The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, ca...
Determining the device width to length ratios has typically been an iterative process for the custom...