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In this era of Deep Sub-Micron (DSM) technologies, interconnects are becoming increasingly important as their effects strongly impact the integrated circuit (IC) functionality and performance. Moreover, logic block size is no longer determined exclusively by total cell area, and is often limited by wiring resources, yet synthesis optimization objectives are focused on minimizing the number and size of library cells. Methodologies that incorporate congestion within the logic synthesis have been proposed in the past. However, in [15] and [16] it was demonstrated that predicting the true congestion prior to layout is not possible, since different layout regions can have very different routing demands, and the effectiveness of any congestion minimization approach can only be evaluated after routing is completed within the assigned die size. In these works, congestion minimization efforts at the synthesis level are controlled by means of a global weightin